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BERTScope® BSA Series

Bit Error Rate Tester

The Confidence of a BERT with the Insight of an Oscilloscope

The BERTScope Bit Error Rate Tester Series provides a new approach to signal integrity measurements of serial data systems. Perform bit error ratio detection more quickly, accurately, and thoroughly by bridging eye diagram analysis with BER pattern generation. The BERTScope Bit Error Rate Tester Series enables you to easily isolate problematic bit and pattern sequences, then analyze further with seven types of advanced error analysis that deliver unprecedented statistical measurement depth
Features & Benefits
  • Pattern Generation and Error Analysis, High-speed BER Measurements up to 28.6 Gb/s
  • Integrated, Calibrated Stress Generation to Address the Stressed Receiver Sensitivity and Clock Recovery Jitter Tolerance Test Requirements for a Wide Range of Standards
    • Sinusoidal Jitter to 100 MHz
    • Random Jitter
    • Bounded, Uncorrelated Jitter
    • Sinusoidal Interference
    • Spread Spectrum Clocking
    • PCIe 2.0 & 3.0 Receiver Testing
    • F/2 Jitter Generation for 8xFC and 10GBASE-KR Testing
    • IEEE802.3ba & 32G Fibre Channel Testing
  • Electrical Stressed Eye Testing for:
    • PCI Express
    • 10/40/100 Gb Ethernet
    • SFP+/SFI
    • XFP/XFI
    • OIF/CEI
    • Fibre Channel (FC8, FC16, FC32)
    • SATA
    • USB 3.0
    • InfiniBand (SDR, QDR, FDR, EDR)
  • Jitter Tolerance Compliance Template Testing with Margin Testing
  • Fast Input Rise Time / High Input Bandwidth Error Detector for Accurate Signal Integrity Analysis
  • Physical Layer Test Suite with Mask Testing, Jitter Peak, BER Contour, and Q-factor Analysis for Comprehensive Testing with Standard or User-defined Libraries of Jitter Tolerance Templates
  • Integrated Eye Diagram Analysis with BER Correlation
  • Optional Jitter Map Comprehensive Jitter Decomposition – with Long Pattern (i.e. PRBS-31) Jitter Triangulation to Extend BER-based Jitter Decomposition Beyond the Limitations of Dual Dirac TJ, DJ, and RJ for a Comprehensive Breakdown of Jitter Subcomponents
  • Patented Error Location Analysis enables Rapid Understanding of your BER Performance Limitations and Assess Deterministic versus Random Errors, Perform Detailed Pattern-dependent Error Analysis, Perform Error Burst Analysis, or Error-free Interval Analysis 
  • Design Verification including Signal Integrity, Jitter, and Timing Analysis
  • Design Characterization for High-speed, Sophisticated Designs
  • Certification Testing of Serial Data Streams and High Performance Networking Systems
  • Design/Verification of High-speed I/O Components and Systems
  • Signal Integrity Analysis – Mask Testing, Jitter Peak, BER Contour, Jitter Map, and Q-factor Analysis
  • Design/Verification of Optical Transceivers
Quick Selector Guide
Model Description Max Bit Rate
BSA85C Bit Error Ratio Analyzer 8.5 Gb/s
BSA125C Bit Error Ratio Analyzer 12.5 Gb/s
BSA175C Bit Error Ratio Analyzer 17.5 Gb/s
BSA286C Bit Error Ratio Analyzer 28.6 Gb/s